Course Details in 2021/22 Session

Module Title	LM Digital Design
School	School of Engineering
Department	Elec, Elec & Sys Engineering
Module Code	04 30054
Module Lead	Dr S.F. Quigley
Level	Masters Level
Credits	20
Semester	Semester 2
Pre-requisites
Co-requisites
Restrictions	None
Exclusions
Description	1. To briefly revise core skills in digital design such as Boolean algebra, K-maps, logic gates and flip-flops. 2. To introduces finite state machine topologies and design processes. This includes both synchronous and asynchronous machines. 3. To give students practical experience of designing synchronous and asynchronous finite state machine on programmable devices. 4. To introduce FPGA’s: Architectures, targeting for synthesis. 5. To introduce VHDL. Basic concepts of HDLs. Design entities. Sequential and concurrent execution. Signals and variables. Process statements. Guarded blocks. Data types in VHDL. 6. To reinforce the student learning experience using hands-on implementations of digital circuits developed by the students
Learning Outcomes	By the end of the module students should be able to: Design combinatorial and sequential circuits efficiently. Define and conduct test procedures for testing digital circuits. Perform hierarchical, modular top down designs of logic systems using VHDL. Produce synthesisable VHDL for the custom digital circuitry of an embedded system. Partition, place and route an FPGA using commercial tools. Program and test an FPGA using commercial evaluation boards. Explain and create designs that imaginatively accommodate the limitation of current FPGA architectures. Demonstrate advanced VHDL design skills.
Assessment	30054-01 : Final Module Mark : Mixed (100%)
Assessment Methods & Exceptions	Laboratory logbooks and Coursework assessment (50%) over Easter vacation May/June Examination (50%)
Other
Reading List